Minimization of Area in Low-Resistance MOS Switches
نویسندگان
چکیده
Several different layout schemes that are useful for implementing low resistance switches with MOS transistors are discussed and characterized. A comparison of the area required for implementing a switch with a standard alternating bar approach is made with layouts using waffle structures, serpentine structures, and modified waffle structures. Analytical design equations for these non-conventional geometries are introduced. The comparisons show that in typical processes, area reductions of over 40% are readily achievable with the modified waffle structures.
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